Senior Hardware Validation & SI Correlation Engineer
Core
Validating high-speed electrical interfaces and system-level hardware for next-generation AI server systems to ensure flawless performance between simulation and silicon.
Role type
Senior Hardware Validation & SI Correlation Engineer
Builds
AI server systems with PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces
Domain
Data center hardware / AI infrastructure / High-speed digital design
Deliverable
production ML models
Required skills
Signal Integrity (SI) modeling and measurement, EM simulation (Ansys HFSS/SIwave, Cadence Sigrity), high-speed protocol physical layers (PCIe, IEEE 802.3), low-speed control buses (I2C, SPI), Python scripting, oscilloscope/VNA usage, power integrity correlation
Preferred skills
GPU/TPU module validation, NVLink or CXL interconnect expertise, automated test framework development, transaction- and link-layer PCIe/DDR5 knowledge
Technologies
Ansys HFSS, Cadence Sigrity, Keysight ADS, Python, TCL, Pandas, NumPy
Responsibilities
Correlate pre- and post-layout SI simulations with physical lab measurements, validate housekeeping/control buses (I2C, SPI, eSPI, UART, SMBus), author Hardware Validation Plans (HVP), build Python automation scripts for data collection from VNAs/BERTs/oscilloscopes
Seniority
Senior, hands-on IC
