Analog Layout Designer
Core
Analog layout designer providing onsite support for advanced nodes, working with global layout and design team.
Role type
Senior IC analog layout designer
Builds
Block level and IP level analog layouts for SerDes, ADC/DAC, PLL, and top-level integration
Domain
Semiconductor design, deep sub-micron processes (FinFet preferred)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog or RF layout design, floorplanning, DRC/LVS debugging, antenna error resolution, ESD/latch-up/EM analysis, Cadence tools, TSMC processes
Preferred skills
FinFet process experience, top-level integration expertise
Technologies
Cadence, TSMC
Responsibilities
Work independently on block and IP level analog layout design, coordinate with circuit designers and layout teams, determine methods and procedures for new assignments, coordinate activities of other personnel as Team Lead
Seniority
Senior, hands-on IC with team lead responsibilities
