CPU Design Verification Engineer
Core
Develop and execute verification plans to validate Altera's RISC-V processor family logic against architectural and microarchitectural specifications.
Role type
Senior IC CPU Design Verification Engineer
Builds
RISC-V processor family
Domain
Semiconductor / CPU Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM-based testbench development, System Verilog, Verilog, VHDL, RISC-V ISA knowledge, coverage-driven verification, assertion-based verification, AMBA protocols, simulation/debug tools, Python/Perl/Tcl scripting
Preferred skills
None stated
Technologies
Synopsys VCS, Cadence Xcelium, Mentor Questa, Python, Perl, Tcl
Responsibilities
Develop and execute sophisticated verification plans; Create scalable, reusable verification environments using UVM; Perform in-depth functional coverage analysis; Execute complex system-level simulations; Debug and perform root-cause analysis of issues; Develop automation scripts and tools; Partner with CPU architects and RTL developers; Maintain and enhance verification infrastructure; Document comprehensive verification strategies; Contribute to CPU architecture and microarchitecture feature definition
Seniority
Senior, hands-on IC
