RTL Design Engineer
Core
Lead digital design and verification of analog mixed-signal (AMS) and I/O subsystems, including advanced AI programs on leading-edge nodes.
Role type
Senior RTL Design Engineer (AMS/IO)
Builds
Digital architecture and verification strategies for complex AMS and IO subsytems
Domain
Semiconductor / Analog Mixed-Signal / Digital Design
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog RTL design, digital implementation flow (RTL synthesis to timing closure), timing analysis (Primetime), Liberty model generation, DFT insertion (Tessent), Perl/Python/Tcl scripting, formal verification (Synopsys Formality/Cadence Conformal), block-level and SoC-level timing constraints
Preferred skills
Transistor-level circuit behavior understanding, Cadence Schematic/Layout, SPICE/Spectre simulation, advanced FinFET process nodes expertise
Technologies
Verilog, SystemVerilog, Primetime, Tessent, Synopsys Formality, Cadence Conformal, Perl, Python, Tcl, Cadence Schematic, SPICE, Spectre
Responsibilities
Define digital architecture and verification strategies for complex AMS and IO subsytems; Design, synthesis, and verification of Verilog/SystemVerilog RTL; Analysis, debug, and resolution of Lint and CDC issues; Design convergence to timing closure utilizing RTL optimization strategies; Conduct formal verification of design; Generate timing constraints for Synthesis and STA; Drive comprehensive test plans; Create and maintain detailed specification, design, and verification documentation
Seniority
Senior, hands-on IC