SoC Design Verification Lead
Core
Lead SoC architecture verification including creating verification strategy, developing test cases and test benches using UVM methodology to enable effective verification of full chip and/or system functionality.
Role type
SoC Design Verification Lead
Builds
SoC verification environments and test plans for full chip and subsystem validation
Domain
Semiconductor / SoC Design / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, System Verilog, formal verification, gate-level simulation, power-aware simulation, FPGA design verification, post-silicon debugging, coverage closure, cross-functional coordination
Preferred skills
Linux/Unix scripting, Perl, Python, ARM-based SoC verification, PCIe/Ethernet/USB/TSN protocols, Design for Debug (JTAG, High speed USB, PCIe based debug)
Technologies
UVM, System Verilog, Perl, Python, Linux, Unix, FPGA, JTAG
Responsibilities
Lead pre-silicon verification strategy and execution for SoC verification; Perform functional logic verification at multiple levels (block, subsystem and full chip); Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment; Document, review, and execute the verification strategy plan on different methodologies/techniques; Execute verification plans and define and run system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs; Replicate, root causes, and debug post-si issues in the pre-silicon environment; Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Seniority
Senior, hands-on IC
