FPGA DDR and IO Subsystem Architect
Core
Define and drive the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera's FPGA product portfolio.
Role type
Senior IC FPGA DDR and IO Subsystem Architect
Builds
High-performance, power-efficient FPGA platforms for cloud, communications, automotive, industrial, and edge AI applications
Domain
Semiconductor / FPGA / High-Speed Memory & IO
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design, ASIC design flows, synthesis, static timing analysis (STA), Verilog, SystemVerilog, C++, Python, DDR4/DDR5/LPDDR4/LPDDR5 controller/PHY/subsystem design, silicon architecture definition, micro-architecture development, system-level trade-off analysis, cross-functional collaboration, signal integrity, power integrity, timing closure, high-speed interface validation
Preferred skills
FPGA architectures, programmable IO subsystems, memory controller + PHY co-architecture integration, EDA/software tool flow optimization, advanced packaging technologies, multi-die integration, silicon bring-up, lab characterization, customer debug
Technologies
Altera Quartus, DDR5, LPDDR5, MIPI, LVDS, ONFI
Responsibilities
Develop architecture for High-Speed External Memory Interfacing and General IO Silicon Subsystem; Define subsystem-level specifications and detailed micro-architecture; Own the solution lifecycle from concept to production release; Drive architectural trade-off analysis across PPA, cost, scalability, and reliability; Lead technical reviews and provide guidance across design, verification, packaging, and software teams; Analyze competitive implementations to identify differentiation opportunities; Engage with strategic customers to influence future product roadmaps
Seniority
Senior, hands-on IC with technical leadership
