Research Fellow (Semiconductor Advanced Packaging)
Core
Develop and validate low-temperature Cu/dielectric hybrid bonding flows for fine-pitch, high-density interconnects to enable manufacturable 3D-integration solutions.
Role type
Research Fellow (Semiconductor Advanced Packaging)
Builds
Wafer-level process flows, prototype stacks (interposer/test-chip), and reliability data for 3D integration.
Domain
Semiconductor manufacturing / Advanced Packaging / Materials Science
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cu interconnect process development, hybrid bonding, cleanroom operations, materials selection, process optimization, failure analysis, reliability testing, statistical design of experiments (DoE), technical reporting
Preferred skills
Python, Matlab, tool vendor collaboration
Technologies
SEM, TEM, XPS, AFM, optical profilometry, electrical probing, thermal cycling, HTS, electrical stress
Responsibilities
Develop and run Cu–Cu hybrid bonding flows; optimize process windows (pressure/temperature/anneal/surface activation); characterize materials and interfaces; validate reliability and scalability via thermal cycling/HTS/electrical stress; produce technical reports and coordinate with partners
Seniority
Mid-level Research Fellow, hands-on IC
