Principal High Speed Clocking Design Engineer
Core
Lead high-speed analog/mixed-signal circuit design for memory product IPs (DDR, LPDDR), focusing on critical clocking blocks and data path specifications.
Role type
Principal High Speed Clocking Design Engineer (Analog/Mixed-Signal IC)
Builds
High-speed analog and digital blocks for memory interface chips
Domain
Semiconductor / Memory Interface / High-Speed Analog Design
Deliverable
production ML models | product features
Required skills
PLL/VCO/PI design, high-speed analog/mixed-signal circuit design, memory clock tree design, DDR5 specifications, design tradeoff analysis, bias/op-amp/LDO principles, pre-silicon verification flow, silicon bring-up and characterization
Preferred skills
DLL architectures, data buffer architectures, bandwidth peaking approaches, development flow definition
Technologies
DDR, LPDDR, PLL, VCO, PI, DLL, LDO
Responsibilities
Own critical clocking blocks (PLL, VCO, PI), design and simulate high-performance high-speed circuits, create high-level models for tradeoff analysis, define architecture and design plan with digital/system teams, create floor plan and collaborate with layout team, document analysis to verify timing parameters, work with lab/system teams for test plan and silicon bring-up, disseminate applicable standards, mentor junior designers, contribute to development flows
Seniority
Principal, hands-on IC design with mentorship