Senior ASIC Verification Engineer, Lund
Core
Pre-silicon verification of in-house developed hardware IPs and subsystems (SoCs) using simulation and formal methods to ensure correct functionality before tape-out.
Role type
Senior ASIC Verification Engineer
Builds
Pre-silicon verified hardware IPs and subsystems for ARTPEC SoCs
Domain
Semiconductor / Hardware Design / SoC Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog HDL, SoC architecture, multi-clock domain design, Python/Tcl scripting, embedded microprocessor verification
Preferred skills
Formal verification, Clock domain crossing verification, Power aware verification, Transaction Level Modeling (TLM), SystemC
Technologies
SystemVerilog, UVM, Python, Tcl, SystemC
Responsibilities
Develop and maintain advanced verification flows and environments, debug and identify potential problems in hardware designs, investigate new verification technologies or evaluate new tools
Seniority
Senior, hands-on IC
