ASIC Design Engineering Manager, Lund
Core
Lead the ASIC Design team to develop next-generation ARTPEC SoC/ASIC designs for real-time image processing, video compression, and computer vision in security cameras.
Role type
Senior IC ASIC Design Engineering Manager
Builds
High-performance, low-power, secure SoC/ASIC designs (ARTPEC) for network and surveillance cameras
Domain
Semiconductor hardware design / Video surveillance / Computer vision
Deliverable
production ML models | product features
Required skills
ASIC design leadership, FPGA design oversight, architectural oversight, strategic technical direction, team coaching and development, project planning and budgeting, process and methodology development, cross-functional collaboration
Preferred skills
Experience in advanced R&D environments, ability to motivate and visualize direction, multi-site department management
Technologies
ARTPEC, SoC, ASIC, FPGA
Responsibilities
Lead, coach, and develop a team of ASIC and FPGA engineers; drive strategic technical direction and align with product roadmap; manage planning, budgeting, and resource allocation; lead organizational and process development; participate in cross-functional project steering groups
Seniority
Senior, hands-on IC with management responsibilities
