Staff RTL Design Engineer - Cache Subsystem
Core
Architect, design, and implement high-performance cache subsystems for RISC-V CPU cores, optimizing microarchitecture and physical design for frequency, area, and power goals.
Role type
Staff RTL Design Engineer (Cache Subsystem)
Builds
High-performance RISC-V CPU cores and cache subsystems
Domain
Semiconductor / CPU Design / RISC-V Architecture
Required skills
Cache subsystem architecture, Multi-level coherent cache design, TileLink/interconnect architecture, RTL design (Verilog/System Verilog/VHDL), Microarchitecture development, Physical design optimization, Verification planning
Preferred skills
RISC-V architecture, Scala/Chisel, UVM/Formal verification, Object-oriented/functional programming
Technologies
Verilog, System Verilog, VHDL, TileLink, RISC-V, UVM, Chisel, Scala
Responsibilities
Architect and implement new high-performance cache subsystems in RISC-V CPU core generators, Develop microarchitecture specifications and documentation, Execute sandbox verification and collaborate on verification test plans, Collaborate with physical implementation teams to optimize design for frequency/area/power, Work with performance modeling teams for optimization
Seniority
Staff, hands-on IC
