Senior IP Verification Engineer(IOMMU-N)
Core
Develop and maintain verification environments for IOMMU-N IP blocks to ensure functional correctness and coverage closure for SiFive's RISC-V compute platforms.
Role type
Senior IC IP Verification Engineer (IOMMU-N)
Builds
Verification environments and test plans for IOMMU-N IP
Domain
Semiconductor / Chip Design / RISC-V / IOMMU
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, constrained-random verification, root cause analysis, coverage closure, Python/Perl scripting, CPU micro-architecture knowledge, bus interface protocols (AXI, AHB, PCIe), third-party VIP integration
Preferred skills
OVM, VMM, x86/ARM architecture knowledge
Technologies
Verdi, SimVision, System Verilog, UVM, Python, Perl, C/C++, AXI, AHB, PCIe
Responsibilities
Analyze architectural specifications to define verification strategies and create comprehensive test plans; Design and implement scalable, reusable, and constrained-random verification environments; Write complex sequences and constrained-random tests to stress-test the IP; Perform deep-dive root cause analysis on RTL design failures and testbench issues; Define and track functional and code coverage metrics using covergroups and coverpoints
Seniority
Senior, hands-on IC
