Sr Staff Engineer, Power Integrity (PI), Signoff Lead
Core
Primary technical authority for IR drop and power delivery aspects of high-speed CPUs, defining sign-off criteria and automating power analysis flows.
Role type
Senior Staff IC Power Integrity Engineer (Signoff Lead)
Builds
High-performance compute architectures (high-speed CPUs)
Domain
Semiconductor chip design / Physical Design / Power Integrity
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
IR signoff criteria definition, Ansys RedHawk, Power Grid (PG) design, bump placement, PrimeTime-PX (PTPX) flow, low power implementation techniques
Preferred skills
3D IC design, package-silicon co-design
Technologies
Ansys RedHawk, PrimeTime-PX
Responsibilities
Define dynamic and static IR sign-off criteria and margins; Architect power-density-aware Power Grid designs; Spearhead automation of static and dynamic IR readouts; Lead PrimeTime-PX flow development for power readouts
Seniority
Senior Staff, hands-on IC with strategic ownership
