CPU Design Verification Engineer
Core
Own verification strategy, methodology, and execution for major out-of-order (OOO) CPU core blocks, driving coverage and sign-off while acting as a technical leader.
Role type
Senior IC CPU Design Verification Engineer (OOO cores)
Builds
RISC-V processor cores for high-performance compute applications
Domain
Semiconductor / CPU Design / Computer Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, OOO micro-architecture, RTL design, assertion-based verification (SVA), coverage modeling, debug of complex hardware failures, mentorship
Preferred skills
Experience with fetch/decode, rename/issue queues, ROB/retirement, LSU/atomics, caches/TLBs/MMU, multi-core coherence protocols
Technologies
System Verilog, UVM, SVA, RISC-V
Responsibilities
Architect and implement System Verilog/UVM testbenches for OOO cores; define coverage models and sign-off criteria; lead debug of complex OOO failures like hazards and memory ordering violations; mentor junior DV engineers; translate ISA and micro-architecture specs into verification plans.
Seniority
Senior, hands-on IC with mentorship responsibilities
