Senior Staff Design Verification Engineer – Coherent Interconnect
Core
Lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs, focusing on coherent data movement, protocol correctness, and subsystem integration.
Role type
Senior Staff individual-contributor design verification engineer
Builds
High-performance SoCs with cache-coherent interconnects (CHI, ACE, CXL)
Domain
Semiconductor / Chip Design / Computer Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, cache-coherent systems, on-chip interconnects, CHI/ACE/CXL/AXI protocols, Python scripting, test plan creation, coverage modeling, debug workflows
Preferred skills
Formal verification, emulation/FPGA-assisted debug, protocol-conversion subsystems, technical leadership
Technologies
SystemVerilog, Python, CHI, ACE, CXL, AXI
Responsibilities
Own verification planning and execution for a scalable cache-coherent interconnect subsystem; Define verification strategy, test plans, environments, and closure criteria; Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; Drive verification of subsystem behavior across interface boundaries and bridge paths; Create high-value directed and constrained-random scenarios; Partner with architecture, RTL, and software teams to close ambiguities; Debug failures and isolate root causes; Contribute to methodology and infrastructure improvements; Mentor engineers and raise verification quality
Seniority
Senior Staff, hands-on IC
