Staff Engineer, Low Power Verification & Formal Equivalence
Core
Lead low power verification and formal equivalence signoff methodologies for advanced high-performance RISC-V processor designs.
Role type
Staff Engineer, Low Power Verification & Formal Equivalence
Builds
Static low power checks and formal verification flows for RTL-to-GDSII design signoff
Domain
Semiconductor chip design (ASIC/SoC), RISC-V architecture, Low Power Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UPF (Unified Power Format) architecture and coding, Static low power verification (RTL and post-PNR), Logical Equivalence Checking (LEC), Formal Equivalence tools, Power Management library cells (ISO, LS, AON, Retention), ASIC/SoC design flow knowledge
Preferred skills
Backend Physical Design (PD) flow knowledge, Scripting (TCL, Python, Perl) for flow automation
Technologies
Synopsys VC Low Power (VCLP), Synopsys Formality, UPF, RTL, GDSII, ECO flows
Responsibilities
Own static low power verification checks across design hierarchy, Architect and automate UPF coding and deployment, Drive complete Formal Equivalence Checking flow from RTL to post-route, Provide optimal UPF and equivalence solutions considering Physical Design limitations
Seniority
Senior, hands-on IC
