Senior Lead Engineer - SoC Design Verification
Core
Architect, develop, and maintain UVM-based and C-based verification environments for RTL functional verification of in-vehicle networking devices.
Role type
Senior IC SoC Design Verification Engineer
Builds
High-reliability automotive networking chips (SoC)
Domain
Automotive electronics / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and testbenches
Required skills
UVM, System Verilog, C/C++, Perl, Python, SVA Assertions, Functional Coverage, Directed and Constrained Random Testing, Low Power Verification (UPF/CPF), Regression Testing, Debugging
Preferred skills
FPGA Prototyping, Formal Verification, Gate-level Timing Simulation
Technologies
System Verilog, UVM, C, Perl, Python, GIT, Jira, Confluence
Responsibilities
Create verification architecture and test plans; Develop UVM components (Agents, Scoreboards, Environments); Drive closure of verification metrics; Debug RTL and Gate-level netlists; Collaborate with Design, Architecture, and Firmware teams.
Seniority
Senior, hands-on IC
