Senior Lead Engineer - SoC Design Verification
Core
Architect, develop, and maintain UVM-based and C-based verification environments for RTL functional verification of in-vehicle networking devices.
Role type
Senior individual-contributor SoC design verification engineer
Builds
Verification environments, testbenches, and test sequences for automotive networking SoCs
Domain
Automotive electronics / SoC design verification
Required skills
System Verilog, UVM, C, C++, Perl, Python, SVA Assertions, Functional Coverage, Directed Testing, Constrained Random Testing, Low Power Verification (UPF/CPF), Regression Testing, Debugging
Preferred skills
FPGA Prototyping, Gate-level timing simulation, Formal verification
Technologies
System Verilog, UVM, C, C++, Perl, Python, GIT, Jira, Confluence
Responsibilities
Create robust verification architecture and test plans; Develop UVM components (Agents, Scoreboards, Environments) and test sequences; Drive closure of verification metrics; Develop C testcases for HW-FW simulation; Debug RTL and gate-level netlists
Seniority
Senior, hands-on IC
