Digital IP Principal Verification Engineer
Core
Define and execute digital functional verification strategies for IP or sub-systems to ensure no functional faults exist per product architect specifications.
Role type
Principal IC verification engineer (digital IP)
Builds
Verified IP blocks and sub-systems for semiconductor products
Domain
Semiconductor / Digital IP / SoC
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Verilog, test planning, testcase generation, testbench development, simulation, debugging, formal verification, code coverage analysis
Preferred skills
Python, C/C++, Perl, TCL, ARM AMBA protocols, RTL design, synthesis, static checkers
Technologies
System Verilog, UVM, SVA, Python, C/C++, Perl, TCL, formal verification tools
Responsibilities
Define IP verification plans based on requirements and industry standards; Write stimulus, random test scenarios, and algorithmic/directed testcases; Develop SystemVerilog Assertion (SVA) cover properties; Create and maintain verification environments including monitors, drivers, and response checkers; Debug failing testcases to identify root causes; Analyze functional coverage results to define additional test scenarios; Perform assertion-based formal verification of blocks and IPs.
Seniority
Principal, hands-on IC
