Senior Design Verification Engineer
Core
Defining and executing verification plans for digital IP components (DDR, display controllers, high-speed serial links, DMAs, memory controllers) to ensure pre-silicon quality and bug-free designs.
Role type
Senior IC design verification engineer (digital IP)
Builds
Digital IP components for automotive microprocessors, application processors, microcontrollers, and networking products
Domain
Semiconductor / Digital Integrated Circuits
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, SVA, test planning, testcase generation, simulation, debug, formal verification
Preferred skills
Python, C/C++, Perl, TCL, ARM AMBA protocols, RTL coding, synthesis, static/formal checkers
Technologies
System Verilog, UVM, SVA, formal verification tools
Responsibilities
Defining and writing IP verification plans based on requirements; Creating intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases; Defining and writing System Verilog Assertion (SVA) cover properties; Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs; Developing and maintaining verification environments including scripts and Make files; Debugging failing testcases to determine source of failure; Collecting and analyzing code and functional coverage results; Performing assertion-based formal verification
Seniority
Senior, hands-on IC
