Senior Digital IP Verification Engineer (f/m/d)
Core
Pre-silicon verification of AI/ML processing blocks, RISC-V processors, and digital IPs for automotive microprocessors and application processors.
Role type
Senior IC digital IP verification engineer
Builds
High-quality, zero-defect digital IP components for automotive and networking products
Domain
Semiconductor / Automotive / Networking
Deliverable
production ML models
Required skills
UVM testbench development, RISC-V architecture, AI/ML accelerator verification, AMBA protocols (AHB, AXI, ACE, CHI), memory systems (ROM, RAM, Flash, DDR/LPDDR), Verilog, SystemVerilog, C/C++, Python, Perl, TCL, Shell, directed and constrained-random verification, formal verification, assertion-based verification, metric-driven verification (functional and code coverage), simulation across abstraction levels (RTL, power-aware RTL, gate-level, FPGA, emulation), debugging in pre-silicon and post-silicon environments
Preferred skills
AI-based tools for verification efficiency, conversational German
Technologies
UVM, Verilog, SystemVerilog, C, C++, Python, Perl, TCL, Shell, RISC-V, AMBA, DDR, LPDDR, FPGA, emulation platforms
Responsibilities
Define and develop comprehensive IP verification plans based on industry standards and product requirements; Architect, develop, debug, and maintain UVM-based verification environments for RTL simulation; Develop testcases including stimulus generation and assertion-based verification; Run simulations across multiple abstraction levels; Execute regressions, analyze results, and drive closure of functional and code coverage; Identify issues, debug failures, and contribute to continuous improvement of verification methodologies and flows
Seniority
Senior, hands-on IC
