Physical Design engineer
Core
Define and develop Physical Design methodology for mixed-signal SoC and IP on low geometry nodes (5/14/16/28/40nm), ensuring timing, power, and signal integrity closure.
Role type
Senior IC physical design engineer (SoC/Physical Implementation)
Builds
Production-ready mixed-signal SoCs and IP blocks
Domain
Semiconductor / VLSI / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (SoC/Physical Implementation)
Required skills
SoC and IP level Synthesis, UPF, formal verification, floor planning, power planning, IO ring design, Place & Route, DRC, ERC, LVS, ESD analysis, analog/digital interface definition, STA flow development, ECO convergence, mixed-signal SoC physical implementation closure, high-speed PHY/IO/PMU IP integration, low power and area optimization, scripting/automation for physical implementation methodology, EDA tool evaluation and benchmarking
Preferred skills
Technical leadership in physical implementation, flow customization for low power/area objectives, resolving blocking issues with EDA vendors, ISO 26262 compliance experience
Technologies
Cadence tools (PrimeTime, Tempus, Tweaker, PrimeClosure), EDA vendor tools, scripting languages
Responsibilities
Develop and define Physical Design methodology for SoC & IP; Manage tools and flow definition; Ensure compliance with NXP design flow, methodologies, and quality standards (ISO 9001, ISO 26262, CMMI); Drive decision for next set of EDA tool selections; Deploy new tools and resolve blocking issues; Lead team to execute on time and meet low power/area objectives
Seniority
Senior, hands-on IC
