3DIC Memory DTCO Engineer
Core
Design and qualify high-bandwidth SRAM and embedded memory IP for heterogeneous, multi-die 3DIC products used in data center-class ASICs for AI/ML, cloud compute, and networking.
Role type
Senior IC 3DIC Memory DTCO Engineer
Builds
High-bandwidth memory macros, physical implementations, and characterization for chiplet-based 3DIC systems.
Domain
Semiconductor, Data Center, 3DIC, Custom Memory, Advanced Packaging
Required skills
Memory macro architecture, Physical design (floorplanning, placement, power grid), DTCO, Cross-die timing signoff, Signal/Power integrity analysis, DFT/MBIST, Silicon characterization, Low-power techniques, TSV/Hybrid bonding planning
Technologies
TSV, Hybrid bonding, 2.5D/3D packaging, STA, PVT, OCV/AOCV, MBIST, PDK
Responsibilities
Architect high-bandwidth embedded memory for multi-reticle, chiplet-based 3DIC systems; Own physical design and optimization for memory-heavy blocks; Plan power distribution and drive TSV planning; Drive DTCO with process/technology teams; Own cross-die timing signoff across the 3D stack-up; Apply low-power techniques; Run signal/power integrity analysis; Develop and validate DFT/MBIST/repair schemes; Drive silicon characterization, correlation, and debug; Collaborate cross-functionally with process, packaging, and design teams; Evolve internal memory compiler/IP flows and 3DIC-aware design methodologies.
Seniority
Senior, hands-on IC
