Senior Technical Manager - RTL Design Engineer
Core
Design and integrate Register Transfer Level (RTL) logic for ARM-based CPU subsystems and module IP, ensuring front-end checks including synthesis, formal equivalence, CDC, lint, power, and timing constraints.
Role type
Senior Technical Manager - RTL Design Engineer
Builds
RTL designs for ARM-based CPU subsystems and module IP
Domain
Semiconductor, SoC Design, RTL
Required skills
RTL design, ARM CPU subsystem integration, Perl scripting, Synthesis, Formal Equivalence Check, CDC analysis, Lint, Power optimization, Timing constraint checks, Design Verification (DV), Design for Testability (DFT), Static Timing Analysis (STA), Low Power Checks
Technologies
Perl, ARM, RTL
Responsibilities
Design RTL for ARM-based CPU subsystems and module IP; Perform front-end checks including synthesis, formal equivalence, CDC, lint, power, and timing; Integrate RTL designs into larger systems.
Seniority
Senior, hands-on IC
