<Data Center>Wireline & Optical System Algorithm Sr. Engineer/Technical Manager
Core
Design electrical/optical PHY and transceiver architecture, digital signal processing, and high-speed SerDes algorithms for wireline and optical systems.
Role type
Senior IC algorithm engineer / Technical Manager
Builds
Ethernet PHY and transceiver architectures, high-speed SerDes interfaces
Domain
Telecommunications / High-speed digital signal processing
Required skills
IEEE 802.3 Ethernet standards, PHY architecture, transceiver design, digital signal processing, mixed-signal design, system simulation, SerDes design, standardization contributions
Responsibilities
Design electrical/optical PHY and transceiver architecture; Develop digital signal processing algorithms for mixed-signal design; Create system simulation models for pre-silicon verification; Design and simulate high-speed SerDes interfaces; Contribute to standard organizations
Seniority
Senior, hands-on IC