LPDDR PE Backend DFT Engineer
Core
Define DFT architecture and test strategies for high-performance mobile DRAM (LPDDR), ensuring testability, yield, and quality from design through mass production.
Role type
Senior IC DFT Engineer (Backend Test)
Builds
Production-ready test programs, patterns, and strategies for mobile DRAM chips.
Domain
Semiconductor manufacturing / Memory (DRAM) / Test Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Backend test methodology, BIST/BOST development, SCAN TEST circuit testing, Verilog simulation, statistical data analysis, scripting for automation, electrical failure analysis, yield improvement analysis, circuit design fundamentals, LPDDR DRAM knowledge.
Preferred skills
AI application in engineering workflows, Japanese language proficiency.
Technologies
Synopsys TestMax, Verilog, statistical analysis tools, in-house engineering equipment.
Responsibilities
Lead feasibility studies and develop test methodologies for new products; improve backend testing coverage and quality for Mobile DRAM; collaborate with DFT/TSE/PE teams to review and sign off backend test program releases; develop testing patterns to enhance efficiency and quality; utilize engineering equipment for product characterization and electrical failure analysis; support new product startup and yield improvement; identify low yield causes through systematic analysis; resolve process/defect issues with engineering groups; define test fixtures for memory/system testing; automate program development using scripting; verify test patterns using Verilog simulations; identify design marginalities and request circuit fixes; leverage AI for operational efficiency.
Seniority
Senior, hands-on IC