Staff Layout Engineer – DPG Layout
Core
Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership.
Role type
Staff Layout Engineer (Analog/Mixed-Signal/Custom Digital)
Builds
Critical analog, mixed-signal, and custom digital blocks for memory and storage solutions
Domain
Semiconductor manufacturing, VLSI design, Analog/Mixed-Signal IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design in advanced CMOS nodes, Cadence Virtuoso (VLE/VXL), Calibre DRC/LVS, layout verification (DRC, LVS, Antenna, Yield, ESD, EM/IR), memory layout (DRAM, SRAM, CAM, OTP), analog fundamentals (matching, symmetry, IR-drop, shielding), AI-driven automation methodologies, SKILL/Python/TCL scripting
Preferred skills
AI-assisted workflows, agentic AI flows, rule-aware automation, floorplanning automation, parasitic estimation automation, design-for-yield practices
Technologies
Cadence Virtuoso, Calibre, SKILL, Python, TCL
Responsibilities
Lead layout implementation using AI-assisted and automated workflows, perform and automate layout verification activities, drive on-time delivery of blocks with risk prediction plans, develop AI-enabled methodologies for semi-automated floorplanning and task elimination, guide and mentor engineers in analog layout fundamentals and automation-first approaches, collaborate with Design, CAD, Verification, and Program Management teams, drive continuous improvement by converting manual bottlenecks into scalable automated flows
Seniority
Staff, technical leadership & mentorship
