DMTS Digital Design Engineer / Chip Lead
Core
Define top-level chip architecture and integrate hard macros with third-party soft IP for high-speed interface innovations.
Role type
Senior IC chip lead (digital design)
Builds
High-speed interface chips integrating custom analog PHYs and digital control functions
Domain
Semiconductor, memory and storage solutions, high-speed interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog RTL design, logic synthesis (DC/Genus), static timing analysis (PrimeTime/Tempus), clock domain crossing strategy, hard/soft IP integration, tape-out sign-off, architecture specification
Preferred skills
High-speed PHY architectures (SerDes, DDR), I2C management bus, DFT strategy (scan insertion, ATPG), OTP/fuse-based trim architectures
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold CDC
Responsibilities
Define top-level chip architecture and partition responsibilities across IP blocks; Author and maintain synthesizable RTL for soft IP control blocks; Develop and own chip-level timing constraints and clock domain crossing strategy; Drive logic synthesis and guide optimization for PPA targets; Manage IP integration agreements and vendor coordination; Own and drive the tape-out checklist sign-off process; Author architecture specifications and interface control documents
Seniority
Senior, hands-on IC lead
