MTS - ESD Design Engineer
Core
Lead ESD architecture and protection strategy for high-speed I/O portfolios including HBM, DDR, and proprietary interfaces to ensure silicon success without compromising performance.
Role type
Senior IC ESD Design Engineer (High-Speed I/O)
Builds
High-bandwidth memory (HBM), DDR, LPDDR PHY I/Os, PCIe, USB, Ethernet, MIPI, and proprietary interfaces
Domain
Semiconductor memory and storage (DRAM, NAND, NOR)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ESD circuit design and protection architecture, high-speed I/O design, mixed-signal chip design, SPICE-based simulation (Spectre, HSPICE), physical layout review, ESD signoff flows, silicon failure analysis, root cause analysis, compact model correlation, substrate/well engineering, latch-up mechanism understanding, high-speed signal integrity
Preferred skills
Experience with HBM, CDM, MM, snapback clamps, rail clamps, diode steering networks, triggered and advanced ESD devices, domain isolation, sequencing protection, PDK engagement, process feature influence
Technologies
Spectre, HSPICE, TLP/VF-TLP, SPICE simulators
Responsibilities
Define and own ESD architecture and protection strategy for high-speed I/O portfolios; Lead ESD–I/O co‑design trade‑off decisions; Perform and guide ESD circuit design and analysis at block and full‑chip level; Establish simulation methodologies for transient ESD stress; Own ESD modeling correlation with device/modeling teams; Lead silicon-level ESD failure analysis across products; Define company-wide layout guidelines for ESD devices; Partner with technology, process, and PDK teams; Serve as the ESD subject-matter guide (SME) across the organization; Mentor and technically develop junior and senior ESD/design engineers
Seniority
Senior, hands-on IC
