Principal/MTS, IO Design Engineering
Core
Design, develop, optimize, and verify high-speed IO and clocking circuits for new DRAM memory products, focusing on equalization, bandwidth extension, and timing analysis.
Role type
Principal/Member of Technical Staff (MTS) IO/Clock Design Engineer
Builds
High-speed IP circuits for Micron's DRAM memory products
Domain
Semiconductor / Memory / High-speed circuit design
Deliverable
production ML models | product features
Required skills
High-speed IO interface design, timing and clocking circuit design, circuit and full-chip level simulation, layout practices for high-speed circuits, silicon validation correlation, process integration knowledge, transistor modeling, scripting (Perl/Python), AI/ML usage
Preferred skills
DRAM circuit design, channel modeling, transceiver noise analysis, equalization techniques, SI knowledge, device physics, CMOS processing, mentoring engineers, Agentic AI
Technologies
EDA tools, AI/ML frameworks, scripting languages (Perl, Python)
Responsibilities
Innovate and verify high-speed IO and clocking circuits; Apply high-speed circuit design techniques to enhance performance evaluation; Develop modeling and simulation methodologies; Collaborate with Product Engineering and SI teams; Work with process integration and transistor modeling teams; Leverage AI-assisted design flow and circuit optimization.
Seniority
Principal, hands-on IC with mentorship