Senior Engineer / Principal Engineer / Member of Technical Staff, Analog / Mixed-signal Design Architect, Next-generation HBM Architecture
Core
Design, simulate, analyze, and optimize the architecture of 3D-stacked, high-performance memories for next-generation HBM products.
Role type
Senior/Principal Analog and Mixed-Signal Design Architect
Builds
High-bandwidth memory (HBM) solutions for emerging AI systems
Domain
Semiconductor / Memory / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Analog and mixed-signal circuit design, transistor-level simulation (FineSim, HSPICE), power delivery analysis, timing/area/power/complexity analysis, architecture trade-off evaluation
Preferred skills
DRAM or 3D-stacked memory device experience, thermal management solutions, scripting (Python, Perl), hardware description languages (Verilog)
Technologies
FineSim, HSPICE, Python, Perl, Verilog
Responsibilities
Design, optimize, and simulate critical analog and/or mixed-signal circuits; Architect and design power delivery for high-performance, stacked memories; Analyze, specify, and prototype on-/off-chip interfaces; Perform timing, area, power, and complexity analysis for high-performance, low-power circuits; Define architectures for improved thermal management; Conduct pathfinding activities for future-generation stacked-memory products
Seniority
Senior/Principal, hands-on IC