Principal Engineer , ASIC Analog Design
Core
Designing and implementing high-speed analog sub-blocks (PLL, DLL, CDR, equalization) for next-generation memory and storage interfaces in deep sub-micron technologies.
Role type
Principal Engineer, ASIC Analog Design
Builds
High-speed PHY blocks for DDR, LPDDR, GDDR, PCIe, and SerDes interfaces
Domain
Semiconductor / Memory & Storage / Analog IC Design
Deliverable
production ML models | product features | infrastructure
Required skills
Analog/mixed-signal CMOS circuit design, High-speed link design (DDR, SerDes), PLL/DLL/CDR architecture, TX/RX equalization (FFE/CTLE/DFE), FinFET technology (10nm and below), System-level modeling (Verilog-A/Python), Layout specification and IP floorplan, Device physics and mismatch analysis, ESD design, Power delivery circuits (Bandgap, LDO), Signal integrity analysis, EDA tool proficiency (Cadence ADE, Spectre, Calibre)
Preferred skills
Mixed-mode simulation, Monte-Carlo methodology, Transistor-level noise analysis, Packaging/Board team collaboration, Lab testing and validation data analysis
Technologies
Cadence ADE, Spectre, Calibre, MATLAB, Verilog-A, Python, FinFET, CMOS
Responsibilities
Drive specification and implementation of analog sub-blocks, Lead layout definition and conform to complex process rules, Participate in silicon bring-up and characterization, Mentor and supervise entry-level engineers, Create block-level specifications based on link budget, Work with packaging and board teams
Seniority
Principal, hands-on IC design with mentorship