Principal Design Engineer
Core
Lead Analog and Mixed Signal design of high-speed memory interface analog components for state-of-the-art DDR memory interface PHYs in leading edge technology nodes.
Role type
Principal Design Engineer (Analog Mixed Signal / Memory)
Builds
High-speed memory interface products (DDR PHYs) for hyperscale computing, 5G, automotive, and aerospace applications.
Domain
Semiconductor IC design, Analog/Mixed Signal, High-Speed SerDes, Memory Interfaces
Deliverable
production ML models | product features
Required skills
Analog/Mixed Signal IC circuit design, High-speed memory interface design (DDR), CMOS SERDES design, Jitter and signal equalization techniques, Circuit simulation and layout using CAD tools, Physical verification
Preferred skills
Experience in <40nm technologies, Lab test experience for silicon evaluation, Cadence tool experience
Technologies
5nm FinFET CMOS, DDR, SerDes, PLL, DLL, CAD tools
Responsibilities
Design high-speed memory interface products at data rates up to 36 Gbps, Design and develop analog/mixed signal IC circuit blocks from concept to verification, Work closely with Physical Design Engineers, Mentor Junior Design Engineers, Collaborate with global teams across different time zones
Seniority
Principal, hands-on IC design with technical direction