Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer, Next-generation HBM Architecture
Core
Design and optimize next-generation 3D-stacked high-bandwidth memory (HBM) architectures for AI workloads.
Role type
Senior IC DRAM Design Engineer (HBM Architecture)
Builds
High-bandwidth memory products for emerging AI systems
Domain
Semiconductor / Memory / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Mixed-signal design, custom analog design, synthesis flows, DRAM circuit design (cell arrays, sense amplifiers, decoders, periphery, IO, power distribution), SPICE simulation (FineSim, HSPICE), floorplanning, design-for-test, design-for-yield
Preferred skills
HBM or stacked memory architecture experience, scripting (Python, Perl), hardware description languages (Verilog), semiconductor device physics
Technologies
FineSim, HSPICE, Verilog, Python, Perl
Responsibilities
Develop novel DRAM circuit architectures for AI workloads; identify circuit bottlenecks and define architectural hypotheses; validate hypotheses via schematic design and SPICE simulation; partner on floorplanning studies; optimize design-for-test and design-for-yield; compose architecture documentation
Seniority
Senior, hands-on IC