Principal HBM Design Architect
Core
Design, simulate, analyze, and floorplan digital and analog DRAM circuits for next-generation high-bandwidth memory (HBM) solutions using 3D stacking and TSV-based integration.
Role type
Senior IC analog/digital mixed-signal design engineer (HBM)
Builds
High-bandwidth memory (HBM) products for data centers and AI applications
Domain
Semiconductor / Memory / High-speed interface
Deliverable
production ML models | product features
Required skills
CMOS circuit design, device physics, schematic entry, HSPICE/FineSim simulation, power distribution analysis, scripting (Python/Tcl/Perl), timing analysis, PVT/parasitic analysis
Preferred skills
DRAM subsystem design, high-speed interface circuits, architectural pathfinding
Technologies
HSPICE, FineSim, Python, Tcl, Perl, 3D stacking, TSV
Responsibilities
Design and optimize data path, ECC, command/control, and high-speed timing structures; evaluate full-chip and block-level functionality; perform timing, area, power, and complexity analysis; conduct pathfinding studies for future architectures; contribute to layout and optimization of memory, logic, and analog circuits; analyze circuit behavior under varying PVT and parasitic conditions; collaborate with build, verification, product engineering, process, and packaging teams.
Seniority
Senior, hands-on IC