Senior Design Verification Engineer
Core
Develop and implement verification plans for high-density DRAM and emerging memory products, ensuring functionality through comprehensive chip and block-level verification.
Role type
Senior Design Verification Engineer (mixed-signal)
Builds
High-density memory chips with complex functionality, ultra-high speed, and advanced low-power technologies
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal verification, HSPICE, VerilogHDL, FINESIM, SystemVerilog, UVM, Debugging, Problem-solving
Preferred skills
SystemVerilog Assertions (SVA), Python, Perl, Project management, Technical leadership
Technologies
HSPICE, VerilogHDL, FINESIM, SystemVerilog, UVM, Python, Perl
Responsibilities
Develop and implement verification plans based on functionality specifications and architectural requirements; Design and maintain test benches and test vectors using digital and analog simulation tools; Debug failures, lead bug tracking, and ensure coverage closure; Collaborate with international teams to create new verification tools and flows; Mentor engineers early in their careers and lead development verification projects
Seniority
Senior, hands-on IC with mentorship responsibilities
