Design Layout Engineer
Core
Design and verify analog, mixed-signal, and custom digital block layouts for high-performance memory and storage solutions (DRAM, HBM) used in AI and high-performance computing.
Role type
Senior IC Layout Design Engineer
Builds
Custom analog/mixed-signal blocks and full chip level integration for DRAM and High Bandwidth Memory
Domain
Semiconductor manufacturing / Memory and Storage / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design, CMOS process expertise (Planar, FinFET), Physical verification (LVS/DRC/Antenna), Block-level layout creation (PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier), Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop), Circuit-layout interaction analysis (speed, capacitance, power, area), Project planning and scheduling
Preferred skills
Tape-out support experience, Multi-project management, Advanced physical verification problem-solving
Technologies
Cadence VLE/VXL, Mentor Graphics Calibre
Responsibilities
Build and develop analog, mixed-signal, and custom digital block layouts; Perform layout verification (LVS/DRC/Antenna) and quality checks; Lead planning, area/time estimation, and scheduling for multiple projects; Collaborate with global engineering teams to ensure project success
Seniority
Senior, hands-on IC