Principal HBM Design Architect
Core
Design and develop high-speed interfaces between DRAM and Base die in HBM cubes, including command/control logic and serialization schemes.
Role type
Principal HBM Design Architect (Senior IC)
Builds
High-bandwidth memory (HBM) products for data centers and AI applications
Domain
Semiconductor / High-performance memory / Analog & Mixed-Signal
Deliverable
production ML models | product features
Required skills
DRAM operation expertise, JEDEC specifications knowledge, analog and mixed-signal circuit design, DRAM command decoding, bank logic design, RAS/CAS chain design, timing/area/power analysis, circuit simulation (FINESIM, HSPICE, Verilog)
Preferred skills
10+ years memory industry experience with MS degree, 15+ years with BS degree, cross-functional design and verification team collaboration
Technologies
FINESIM, HSPICE, Verilog, DDR, LPDDR, GDDR, HBM
Responsibilities
Design DRAM command and control logic; implement serializing and de-serializing schemes; conduct circuit simulations; collaborate on floor planning and testbench; analyze timing/area/power; optimize Memory, Logic, and Analog circuits
Seniority
Principal, hands-on IC with strategy & mentorship