Senior High Speed IO Validation Engineer
Core
Characterization and qualification of high-speed I/Os (PCIe, NVLink, UCIe, USB, UFS, Ethernet) on new silicon for datacenter, AI, and client markets.
Role type
Senior IC validation engineer (high-speed I/O)
Builds
High-volume production GPUs, SoCs, and CPUs
Domain
Semiconductor / High-speed serial interconnects
Required skills
High-speed serial link protocols (PCIe Gen5+, NVLink, UCIe, CXL), SERDES architecture, Signal Integrity (SI) and Power Integrity (PI) fundamentals, Lab instrumentation (DSOs, BERTs, VNAs, protocol analyzers), Python-based test automation, Root-cause analysis across silicon/package/board/firmware
Preferred skills
PCIe Gen5/Gen6 or NVLink validation on production silicon, SERDES or analog circuit design experience, Translating rack-environment conditions to silicon/board characterization, AI productivity tools usage
Technologies
PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet, CoWoS, interposer, substrate, Python
Responsibilities
Own end-to-end characterization and validation of high-speed IO from silicon die through package and board; Develop and execute validation test plans for silicon and SoC-level HSIO features; Drive power characterization and optimization across IO interconnects; Drive systematic root-cause analysis for complex HSIO bugs; Assess manufacturing and yield implications of HSIO margin distributions; Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure
Seniority
Senior, hands-on IC
