VLSI Timing Methodology Intern - Summer 2027
Core
Research and develop compact device and system models to predict silicon timing behavior using Machine Learning and analytical techniques.
Role type
Summer intern VLSI timing methodology engineer
Builds
Large scale internal CAD tools and silicon projection methodologies
Domain
Semiconductor hardware design, VLSI, AI/ML
Deliverable
production ML models
Required skills
Static Timing Analysis, MOSFET device physics, VLSI backend design, Machine Learning, Python scripting
Preferred skills
BSIM device compact models, prior VLSI internship experience, VLSI/CAD design coursework
Technologies
Python, Perl, Tcl, BSIM
Responsibilities
Develop tools to predict and improve silicon performance and reliability; Explore physical effects (IR drop, crosstalk, aging, thermal) influence on timing.
Seniority
Intern
