Senior Chip Design Engineer
Core
Design and implement next-generation Networking Silicon chips, focusing on core units, micro-architecture, and RTL implementation to deliver high-throughput, low-latency communication devices.
Role type
Senior IC chip design engineer (networking silicon)
Builds
Networking silicon chips (high-speed communication devices)
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design, HDL (Verilog/SystemVerilog/VHDL), digital design fundamentals (pipelining, clock domain crossing, arbitration, low-power techniques), synthesis, static timing analysis
Preferred skills
Physical design constraints, backend flow integration
Technologies
Verilog, SystemVerilog, VHDL, Synthesis tools, Static timing analysis tools
Responsibilities
Own micro-architecture definition and RTL implementation of chip blocks; Drive designs through full implementation flow (synthesis, timing closure, lint/CDC, physical design constraints); Collaborate with Architecture, Verification, FW, and Post-Silicon validation teams.
Seniority
Senior, hands-on IC
