ASIC Design Engineer, Tools and Methodology Development
Core
Develop and deploy in-house tools and workflows to support engineering business units, verify common design blocks, and act as a DevOps engineer for automated RTL generation.
Role type
Senior IC ASIC Design Engineer (Tools and Methodology)
Builds
In-house verification tools, automated RTL generation workflows, and IP development environments
Domain
Semiconductor / ASIC Design / EDA Tools
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog, Python scripting, Perl scripting, Unix/Linux shell scripting, Makefiles, Digital design concepts
Preferred skills
ASIC verification, Clocks/Resets design and verification, CDC design/verification flows, Backend flows (Synthesis, Timing)
Technologies
Verilog, Python, Perl, Unix/Linux, Makefiles
Responsibilities
Develop and deploy in-house tools and workflows, Take ownership of tools that verify common design blocks, Act as a DevOps engineer for automated RTL generation, Build new workflows and methodologies for IP development environments
Seniority
Senior, hands-on IC
