Physical Design Engineer (RDSS Intern)
Core
VLSI physical design engineer intern responsible for netlist-to-GDSII flow, floorplanning, placement, routing, and timing/power optimization for NVIDIA chips (GeForce/Tegra/Tesla/Quadro).
Role type
Intern, VLSI Physical Design Engineer
Builds
Physical design flows and chip layouts for NVIDIA GPUs and accelerators
Domain
Semiconductor, VLSI, ASIC/IC Design
Deliverable
production ML models
Required skills
VLSI physical design, floorplanning, placement and routing, timing analysis, power/noise/DFM optimization, physical verification, flow automation, EDA tool usage
Preferred skills
Perl, Python, Tcl, Shell scripting, IC design project experience
Technologies
EDA tools
Responsibilities
Execute physical design from netlist to GDSII, perform floorplanning and power/clock distribution, conduct placement and routing, optimize timing/power/noise/DFM, perform physical verification, automate flows and regression testing, collaborate with EDA vendors, develop in-house tools
Seniority
Intern
