ASIC Physical Design Intern - 2027
Core
Intern role focused on ASIC physical design tasks from RTL freeze to tape-out, including synthesis, verification, and timing closure.
Role type
ASIC Physical Design Intern
Builds
Digital chips for high-frequency, low-power applications
Domain
Semiconductor / IC Design
Deliverable
production ML models
Required skills
IC design knowledge, EDA tool usage (Synopsys DC/PT/Formality, Cadence RC/LEC), Python/TCL scripting, timing analysis, floorplanning, netlist generation
Preferred skills
IC backend implementation experience, flow automation development
Technologies
Synopsys Design Compiler, PrimeTime, Formality, Cadence RC Compiler, LEC
Responsibilities
Chip integration and netlist generation, synthesis and RTL quality check, constraints creation and validation, timing closure and sign-off, flow automation development
Seniority
Intern
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