DPU Performance Validation Engineer
Core
Debug, analyze, and validate performance and functional behavior of NVIDIA silicon devices (DPUs) across single-die and multi-die systems in pre-silicon environments.
Role type
Senior IC DPU Performance Validation Engineer
Builds
NVIDIA DPU product lines
Domain
Semiconductor / Network Silicon Engineering
Deliverable
production ML models | product features
Required skills
ASIC debug, RTL-level analysis, waveform analysis, system-level performance root cause analysis, Python, C/C++, Linux environment
Preferred skills
Performance modeling, traffic generation, architecture studies, modern interconnects (PCIe, Ethernet, CHI), emulation platforms (Palladium, Veloce, FPGA)
Technologies
Palladium, Veloce, FPGA, PCIe, Ethernet, CHI
Responsibilities
Debug and root-cause performance issues in pre-silicon environments; Collaborate with design, verification, architecture, and performance modeling teams; Develop and improve validation methodologies; Automate repetitive debug and validation tasks
Seniority
Senior, hands-on IC
