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Senior DFT - Silicon Validation Engineer

US, CA, Santa Clara💼 Full-time💰 $168,000–$168,000🗓 2026-08-21 → 2026-09-25

Core

Drive end-to-end DFT architecture and methodologies to accelerate post-silicon bring-up, characterization, and yield ramp for complex semiconductor chips.

Role type

Senior IC DFT/Silicon Validation Engineer

Builds

Next-generation ATE test strategies and silicon validation for NVIDIA GPU and SoC products

Domain

Semiconductor / Hardware Design / DFT

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

DFT architecture, silicon debug, bring-up, yield ramp, ATE test strategies, SoC validation, failure root cause analysis

Preferred skills

Perl, Python, Tcl scripting, high-speed protocols, semiconductor process technology, DFT tools

Responsibilities

Collaborate with multi-functional teams on silicon validation, define test strategies for product roadmap, lead early silicon validation for complex SoC, perform chip validation on ATE, debug test content, analyze silicon behavior under various operating conditions, identify failure root causes, ensure strong production ramp

Seniority

Senior, hands-on IC

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