ASIC Physical Design Engineer
Core
Physical design engineering from RTL to GDSII, including timing closure, synthesis, formal verification, and floorplanning for advanced process technologies.
Role type
ASIC Physical Design Engineer
Builds
Integrated circuits (chips) for the largest chip in the world
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL to GDSII flow, STA for hierarchical design, timing closure (partition/full chip), synthesis, netlist quality check, formal verification, chip partition, floorplanning, flow automation, Python/Perl/TCL scripting
Preferred skills
Perl/Python/TCL proficiency, English communication
Technologies
Synopsys (FC/DC/PT/Formality), Cadence (RC compiler/Genus/LEC)
Responsibilities
Perform static timing analysis (STA) for hierarchical designs; create and validate constraints and timing budgets; execute timing closure at partition and full chip levels; handle special timing closure for I/O, test, and clock; perform synthesis and netlist quality checks; conduct formal verification; implement chip partition and floorplan; develop and enhance timing closure flows from pre-layout to post-layout; automate flows and methodologies.
Seniority
Junior to Senior
