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Senior Chip Design Verification Engineer

Israel, Beer Sheva💼 Full-time🗓 2026-04-09 → 2026-09-25

Core

Verification for chip blocks according to specifications under challenging constraints with high orientation to power, area, and performance.

Role type

Senior IC chip design verification engineer (RISC-V)

Builds

High-speed communication devices (Networking Silicon)

Domain

Semiconductor / Networking / RISC-V

Deliverable

production ML models | product features

Required skills

RTL Frontend ASIC Verification, Specman, System level aspects, Power optimization, Area optimization, Performance optimization

Preferred skills

Extensive RTL Frontend ASIC Verification experience, Strong Specman knowledge, System level background

Technologies

Specman, RISC-V

Responsibilities

Verify chip blocks according to specifications, Work on RISC-V processors platform, Collaborate with firmware and global groups

Seniority

Senior, hands-on IC

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