Senior ASIC Engineer, Power Integrity
Core
Designing power delivery and power management solutions for innovative processors in deep submicron technologies to ensure reliability, performance, and stability.
Role type
Senior IC ASIC engineer (power integrity)
Builds
Processor designs and power delivery networks (PDN)
Domain
Semiconductor / Analog and Mixed Signal (AMS) / Power Integrity
Deliverable
production ML models
Required skills
Power integrity modeling and simulation, Analog and digital circuit modeling, System-level simulation, EDA tool usage (Cadence Virtuoso, Allegro, VCS, HSpice, Spectre, Primesim), AMS simulation, Verilog/VerilogA
Preferred skills
Complex PDN modeling (die to platform level), Ansys Siwave/HFSS/Sigrity/Matlab/Simulink/Simplis, Control loops and feedback systems, Scripting (Perl, Tcl, Python, Skill)
Responsibilities
Participate in innovative Processor design in deep submicron technologies, Design innovative power delivery and power management solutions, Build models of analog and digital circuits and systems, Perform detailed block-level and system-level simulations, Mentor junior team members
Seniority
Senior, hands-on IC with mentorship