Senior HBM Architecture & Circuit Design Engineer
Core
Own next-generation HBM core-die architecture and critical DRAM circuit design to optimize bandwidth, power, area, thermal efficiency, and reliability for AI-enabled solutions.
Role type
Senior IC HBM Architecture & Circuit Design Engineer
Builds
Advanced 3D-stacked HBM products and Architecture Reference Designs (ARD)
Domain
Semiconductor / Memory / High Bandwidth Memory
Deliverable
production ML models
Required skills
DRAM architecture design, DRAM circuit design, SPICE-based simulation, PPA trade-off analysis, reliability mechanism design, cross-functional technical execution
Preferred skills
Silicon bring-up, failure analysis, architecture-to-design handoff
Technologies
HSPICE, Spectre, FineSim, PrimeSim
Responsibilities
Define Bank/Bank-Group organization, array partitioning, and datapath; Drive timing closure for row, column, sensing, and datapath paths; Develop and optimize architecture solutions for bandwidth, power, area, thermal, and reliability; Define and validate refresh, row-hammer mitigation, and power-efficient operation schemes; Lead architecture feasibility studies using transistor-level simulation; Develop golden schematics, timing budgets, and verification methodology; Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification, and DFT teams; Support silicon bring-up, characterization, and failure analysis.
Seniority
Senior, hands-on IC