Sr/ Staff Design Engineer/Architect(Datapath), HBM
Core
Architect, design, and optimize high-speed datapath circuitry for next-generation High Bandwidth Memory (HBM) products, focusing on logic-die and core-die architectures to enable industry-leading bandwidth, power efficiency, and reliability.
Role type
Senior IC digital design engineer (HBM datapath)
Builds
High-bandwidth memory (HBM) logic and core dies
Domain
Semiconductor / Memory / High-speed digital design
Required skills
High-speed digital datapath design, Digital schematic build, RTL design, Mixed-signal datapath implementation, Timing closure, Static timing analysis (STA), Multi-channel architecture design, ECC/Parity design, Clocking and gating strategies
Preferred skills
HBM/DRAM architecture knowledge, Layout and floorplanning, Signal integrity and skew control, Advanced process-node challenges
Technologies
HBM, JEDEC standards, RTL, Schematic, STA
Responsibilities
Architect and design HBM read/write datapath across core and logic die, Develop high-speed low-latency datapath circuits for multi-channel HBM, Optimize designs for bandwidth/power/area/timing, Design data reliability features (ECC, redundancy), Collaborate with PHY/verification/layout teams, Drive schematic and RTL implementations, Contribute to design reviews and mentoring
Seniority
Senior, hands-on IC
